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Partner Product

Model 5342-428  (Pentek Inc)
Model 5342-428 is a software radio transceiver suitable for connection to HF or IF ports of a communications system. It features two A/D and two D/A converters with built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane. A unique fabric-transparent crossbar switch bridges numerous interfaces and components on the board with no latency.

Product Highlights

*Complete software radio interface solution *3U VPX form factor *GateFlow IP Core 428, with four high-performance multiband DDCs and one Interpolation Filter, factoryinstalled *Two sets of 18-bit userprogrammable FIR filter coefficients *Decimation range from 2 to 65,536 in steps of 1 *Interpolation range from 2 to 32,768 in steps of 4 *LVDS clock/sync bus for multiboard synchronization

Product Description

A/D and D/A Converter Stages

The front end accepts four full scale

analog HF or IF inputs on front panel MMCX

connectors at +10 dBm into 50 ohms with

transformer coupling into Linear Technology

LTC2255 14-bit 125 MHz A/D converters.

The digital outputs are delivered to the

Virtex-4 FPGA for signal processing or for

routing to other board resources.

A TI DAC5686 digital upconverter (DUC)

and D/A accepts a baseband real or complex

data stream from the FPGA with signal bandwidths

up to 40 MHz.

When operating as an upconverter, it

interpolates and translates real or complex

baseband input signals to any IF center frequency

between DC and 160 MHz. It delivers

real or quadrature (I+Q) analog output

samples at up to 320 MHz to the 16-bit D/A

converter. Output is through a front panel

MMCX connector at +4 dBm into 50 ohms.

If translation is disabled, the DAC5686

acts as an interpolating 16-bit D/A with output

sampling rates up to 500 MHz.

Core 428 Multiband DDCs

The Core 428 downconverter translates

any frequency band within the input bandwidth

range down to zero frequency. The

DDCs consist of two cascaded decimating FIR filters. Each filter is capable of any decimation

from 2 to 256. The decimations of

the first stage filter and the second stage

filter multiply to yield overall decimation

factors up to 65,536. The second stage FIR

may be bypassed for decimations of 256 or

lower. The decimation of each DDC can be

set independently. After each filter stage is

a post filter gain stage. This gain is primarily

used to compensate for bit growth in

the filter at different decimations but may

also be used to amplify small signals after

out of band signals have been filtered out.

The NCO provides over 108 dB spurious-

free dynamic range (SFDR). The FIR

filter is capable of storing and utilizing two

independent sets of 18-bit coefficients.

These coefficients are user-programmable

using RAM structures within the FPGA.

NCO tuning frequency, decimation and

filter coefficients can be changed dynamically.

Four identical Core 428 DDCs are factory

installed in the 5342-428 FPGA. An input

multiplexer allows any DDC to independently

select any of the four A/D sources.

The overal decimation range from 2 to

65,536, programmable in steps of 1, provides

output bandwidths from 50 MHz down to

1.52 kHz for an A/D sampling rate of

125 MHz and assuming an 80% filter.

Core 428 Interpolation Filter

The Core 428 interpolation filter increases

the sampling rate of real or complex baseband

signals by a factor of 16 to 2048,

programmable in steps of 4, and relieves

the host processor from performing

upsampling tasks. The interpolation filter

can be used in series with the DUC’s builtin

interpolation, creating a maximum

interpolation factor of 32,768.

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Wind River, a wholly owned subsidiary of Intel Corporation (NASDAQ: INTC), is a world leader in embedded and mobile software. Wind River has been pioneering computing inside embedded devices since 1981 and its technology is found in more than 500 million products