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Partner Product

Model 6236  (Pentek Inc)
Model 6236 is a dual 14-bit A/D VIM-2 module. It attaches directly to VIMcompatible baseboards and includes a Virtex- II FPGA (Field Programmable Gate Array) as well as optionally available wideband digital receivers.

Product Highlights

*Two low distortion 105 MHz 14-bit A/D converters * Internal or external A/D sample clock to 105 MHz *Advanced Virtex-II FPGA for signal preprocessing *Front panel sync bus *ASIC and FPGA wideband downconverter options

Product Description

Front End

The Model 6236 accepts two analog RF

inputs at +4 dBm full scale into 50 ohms on

front panel SMA connectors.

Each of the two inputs is transformer

coupled and digitized by an Analog Devices

AD6645-105 14-bit A/D converter. The

AD6645 is capable of operating at sample

rates from 30 MHz to 105 MHz.

The A/D converter clock can be driven

from an internal crystal oscillator or from an

external sample clock supplied through

a front panel SMA connector or front panel

sync bus.


The A/D outputs are delivered to a Xilinx

Virtex-II FPGA (Model XC2V1000

standard; XC2V3000 optional) which is

factory configured to perform various

modes of data packing, formatting and

channel selection. The A/D outputs are

connected directly to the FPGA so that

wideband A/D data can be delivered directly

to the DSP board.

Optionally available design kits allow the

FPGA to be configured by the user for

implementation of custom preprocessing

functions such as convolution, framing, pattern

recognition and decompression.

Optional Digital Downconverters

The 6236 offers two different wideband

digital downconverter options, each featuring

a decimation range from 2 to 64.

Option -212 adds two bypassable

Graychip GC1012B downconverter ASICs

with 40 MHz maximum bandwidth for a

100 MHz sample clock, 75 dB stopband

attenuation, 12-bit input and 16-bit output.

Option -421 adds a dual-channel Gate-

Flow Downconverter Installed Core within

the FPGA with 42 MHz maximum bandwidth

for a 105 MHz sample clock, 100 dB

stopband attenuation, 14-bit input, 24-bit

output and programmable filter coefficients.


The front panel clock and sync bus allow

one 6236 to act as a master driving the

sample clock out to a front panel cable bus

using LVDS differential signaling. Multiple

slaves can then be clocked synchronously

with the master.

Front Panel I/O

An optional front panel connector provides

digital input and output for the FPGA.

These lines are available for triggering, synchronizing,

or framing signals. They are also

useful during FPGA algorithm development

for timing and signal probing.

VIM Processor Interface

The FPGA outputs are connected

directly through the VIM mezzanine interface

to the 32-bit synchronous BI-FIFO on the

VIM processor board where it is buffered for

efficient block transfers into the DSP.

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Wind River, a wholly owned subsidiary of Intel Corporation (NASDAQ: INTC), is a world leader in embedded and mobile software. Wind River has been pioneering computing inside embedded devices since 1981 and its technology is found in more than 500 million products